1. Field of the Invention
The present invention relates to a self-test circuit for self-diagnosis incorporated in a memory device and in particular relates to a self-test circuit whereby self-test can be performed utilizing comparatively few input/output terminals. The present invention relates for example to self-test circuits that are suitable for burn-in testing in the wafer processing step.
2. Description of the Related Art
In recent years, memory devices such as dynamic RAM (DRAM) have been increased in capacity and scale. Concomitantly, the cost of the testing step in which inspection for failed bits within the memory is performed using an LSI tester has increased, resulting in increased costs of the memory device.
FIG. 1 is a typical layout diagram of a prior art memory device. FIG. 1 shows a typical layout taking the example of a synchronous DRAM (SDRAM). In the example of FIG. 1, a clock CLK is supplied to clock input buffer 10 from outside, and an internal clock I-CLK is supplied to each circuit block. Also, command input CMD is supplied to command decoder 12 from outside, the decoded external command CMD is latched in command latch circuit 16, and a control circuit 18 controls the circuitry within memory bank MBNK, which is the memory core, in response to this latched external command. Also, addresses A0 to An are supplied to address buffer 14 from outside, and its address EXADD is supplied to memory buffer MBNK.
A memory bank MBNK is divided into, for example, a plurality of memory blocks BLK; in each memory block there are provided a row decoder RDEC, a memory cell array MCA, a sensing amplifier SA, and a column decoder CDEC etc. Furthermore, the memory blocks are connected to a sensing buffer and write amplifier SB/WA through a database DB and are furthermore connected to an input/output terminal DQ through a data input/output circuit DI/O.
Furthermore, although not shown in the drawing, within memory bank MBNK, there are provided redundant cells that are capable of replacing failed bits. Failed bits detected by an operation test are replaced by these redundant cells, and shipped as a passed chip.
In a conventional testing step in which failed bits are detected prior to shipping, an LSI tester supplies from command input terminal CMD, address terminals A0 to An and input/output terminal DQ the operating commands, addresses, and write data etc that are required for testing, and checks whether or not the read data that is output from input/output terminal DQ is the expected data. Consequently, for example when performing a test of whether data 1 can be read or not by writing data 1, the LSI tester performs writing using an active command, write command, reset command, non-select command etc, and performs reading using an active command, read command, reset command, and de-select command etc.
This test step using an LSI tester is usually performed after the LSI chip has been accommodated in the package in the assembly step, which is a later step.
However, in the above defect testing step, it is necessary to employ an LSI tester, and a long time is required due to the increased capacity of memory. It has therefore been proposed to incorporate within a memory device a testing circuit for self-diagnosis, in order to perform the above defect test without using an LSI tester. Such a self-test circuit is called a “Built-In Self-Test (BIST) circuit (hereinbelow referred to simply as BIST circuit).
However, no consensus has yet been reached as to what construction of such a BIST circuit is most suitable. For example, if a BIST circuit is incorporated in a memory device but simply outputs “pass” or “fail” of the test, it is impossible to ascertain the number of failed bits, and so it is not possible to decide whether or not a rescue function utilizing redundant cells can be utilized. If, on the other hand, the BIST circuit stores all the addresses of failed bits, the BIST circuit itself becomes of large scale and so impracticable.
In contrast, the prior art method in which failed products that were incapable of being rescued by redundant cells were excluded by performing a diagnostic test after the subsequent step (assembly step) of the manufacturing step did not make a sufficient contribution to lowering device costs. Rescuing failed products by utilizing redundant cells converts failed products into passed products, and so contributes to lowering of costs to a certain extent. However, if the defect test is performed after the assembly step, the proportion of costs relating to the assembly step of devices that finally end up as failed products is wasted.
In order to solve such problems, it has been proposed to perform the burn-in test (accelerated test) in the preceding step (wafer level) of the manufacturing step. However, the testers for the accelerated test at the wafer stage have only a small number of probes that can be utilized, so it is difficult to perform a complicated function test such as was performed with the conventional LSI tester. It is therefore desirable to incorporate in the memory device a self-test circuit that can be utilized in the burn-in test at wafer level.